Benchmarking
Evaluation of Electromagnetic Software
Revised: June 4, 1997
© Copyright 1994, 1999 Sonnet Software, Inc. All Rights Reserved
Table of Contents
Chapter 1 - Introduction
Chapter 2 - Technical Overview
Chapter 3 - The Stripline Standard
Chapter 4 - The Stripline Standard and Triangular Subsections
Chapter 5 - The Microstrip Standard
Chapter 6 - The Coupled Microstrip Standard
Chapter 7 - Limit Tests
Chapter 8 - Lossy Ground Plane and Lossy Dielectric Tests
Chapter 7 - Limit Tests
Ultra-thin Dielectric | Zero Length Through | Short Length Vias
In this chapter we present several simple tests which take an analysis to basic limits for which exact results are known. Error in these limiting cases indicates that the software developer did not check these cases or that the difficulty is fundamental to the technique and it is not possible to correct.
If your work requires analysis of ultra-thin dielectric layers, the test described in this section is critically important. For example, in GaAs MMIC (Monolithic Microwave Integrated Circuit) design, MIM (Metal-Insulator-Metal) capacitors are used. The dielectric for these capacitors is usually of sub-micron thickness and is formed from silicon nitride. If proper care is not taken in the development of an electromagnetic analysis, this test can fail catastrophically with the resulting analysis unusable for MIM capacitors or other thin dielectric problems.
MIM capacitors have an inherent inductance (in series with both the top and bottom plate) and shunt capacitance (from the bottom plate to ground). This is what results in the need to model these capacitors with electromagnetics. This also means that we do not have an exact theoretical answer at high frequency.
To get around this problem, this limit test simply looks for the parallel plate capacitance at low frequency. If there is a problem with ultra-thin dielectric at high frequency (as is frequently the case), it should also appear at low frequency. Of course, there could be other problems at high frequency, but such problems should be found by application of the other benchmarks described in this document. This benchmark is intended only to find problems directly related to ultra-thin dielectric layers. Since we can easily calculate the parallel plate capacitance of the capacitor, we can compare that with the capacitance which results from the electromagnetic analysis.
This capacitor uses the same general geometry as the microstrip standard. A conceptual side view of the capacitor geometry is shown in Figure7 in Chapter 5. A top view is shown in Figure8 in Chapter 5. A dimensioned drawing is shown below in Figure 11. Since we are considering only the low frequency response of the capacitor, the only critical dimensions of the capacitor are the area (64 x 64 mm), dielectric thickness (0.1 mm) and dielectric constant, 6.8. We choose the dielectric thickness slightly thinner than usually used in order to create a more stringent test.
The substrate dimensions used are 256 x 256 mm, 100 mm thick with a dielectric constant of 12.9 to simulate GaAs. However, at low frequencies, the substrate used is not important. We are concerned only with the correct value of the parallel plate capacitance of the capacitor. All of the above parameters have been selected to represent a typical MIM capacitor.
Figure 11. The test for ultra thin dielectric simply looks at the low frequency capacitance of an MIM capacitor with dielectric thickness of 0.1 m m and relative dielectric constant of 6.8. The substrate has dielectric constant of 12.9 and is 100 m m thick. Substrate characteristics are not critical for this test.
The theoretical parallel plate capacitance of the above capacitor is 2.466 pF. Sonnet was used to calculate the capacitance using a cell size of 16 x 16 mm. At 1 MHz, the calculated capacitance is 2.539 pF, an error of 2.96%. At a cell size of 8 x 8 mm, the calculated capacitance is 2.509 pF, an error of 1.74%. If we were to do a convergence analysis (by calculating the capacitance as we decrease the cell size), we would expect convergence to a value slightly higher (due to fringing capacitance) than the calculated parallel plate capacitance. The above data is consistent with that convergence, and thus this capacitor limit test is passed.
Sonnet evaluated the capacitance by using the lumped model synthesis option. Specifically, Sonnet calculated the S-Parameters of the structure and then automatically synthesized a lumped model which duplicates the calculated S-Parameters.
When evaluating software without a lumped model synthesis feature, it is easier to compare S-Parameters instead of the actual value of capacitance. The magnitude of S21 at 1 MHz corresponding to the theoretical parallel plate capacitance of 2.466 pF is 0.001550 at an angle of almost exactly 90 degrees. Sonnet calculates 0.001595 using a 16 mm cell and 0.001576 using an 8 m m cell size at 1 MHz.
If an analysis fails this evaluation at 1 MHz due to numerical precision problems, it can be performed as high as 1000 MHz, however the additional errors of series inductance and shunt capacitance mentioned at the beginning of this section start to become problems.
To perform this test, simply capture a microstrip (or stripline) through line. In fact, the Stripline standard works well for this test.
To make a zero length through line, just set reference planes from both port 1 and port 2 such that the entire line is de-embedded, i.e., the de-embedding leaves a zero length through line, see Figure 12.
Make sure that any de-embedding length requirements are met. For Sonnet the reference planes should be at least one substrate thickness in length.
The correct answer is S11 = 0.0, S21 = 1.0 at 0.0 degrees. Any difference from this answer is error. Expect to see error if, for example, multiple higher order modes are propagating, or if any other de-embedding assumptions are violated. In fact, by changing the length of the through line (while still de-embedding to zero length), you can check the impact of having a reference plane that is too short.
Over the useful operating frequency range of the transmission line, the error should be just numerical noise left over from the matrix inversion. For example, if we use the Stripline Standard at 16 cells wide and 128 cells long, de-embedded to zero length at 15 GHz with Sonnet, the result is S11 = 8.1 x 10-8 and S21 = 1.0 at 5.7 x 10-5 degrees. Such small numbers fall into the realm of numerical noise.
Figure 12. Top view of the zero length through line.
Note that while this is a necessary test for de-embedding correctness, it is not sufficient. It is entirely possible that an analysis can pass this test while there is still significant error in the underlying electromagnetic analysis or even with the de-embedding algorithm itself. Such problems should become apparent in the evaluating the standards previously described in this document.
If, however, an analysis fails this self-consistency test, the de-embedding algorithm should be considered faulty and, at the very least, a noise floor established below which results should not be considered valid. The noise floor should be at least 6 dB above the noise found with this test.
This limit test can also be applied to coupled lines. Now, all reflection coefficients must be zero and all transmission coefficients between connected ports must be 1.0 at 0.0 degrees and other transmission coefficients zero.
As subsection or mesh size becomes very small, electromagnetic analyses encounter a low frequency limit. The limit usually results from a difference between two large numbers causing a loss of precision. With Sonnet, operated in the default double precision, this limit is encountered when subsection size is about 10-5 wavelengths. The problem is most apparent with very short, small area vias.
To illustrate the problem, we captured a through with a via in the middle as shown in Figure 13. The through line enters on the left at port 1. The via goes up into the air 0.1 micron and then the through line exits on the right at port 2. Cell size is 1 micron square, and the substrate size is 10 microns square. The substrate is 100 microns thick and has a dielectric constant of 12.9. Except for substrate area, these are typical dimensions for a very high resolution analysis of a portion of a GaAs monolithic microwave integrated circuit. The 0.1 micron tall via is on the short side of what can be expected when going from the substrate surface up to the top plate of a capacitor through a thin layer of silicon nitride. This emphasizes the numerical precision problem.
Figure 13. Top view of the short length via. At low frequency, it should be a through.
At 2.0 GHz without de-embedding, Sonnet gives an S21 phase of 16.67 degrees, much too long. From the physical length and assuming an effective dielectric constant of 7.0, we would expect a phase of about 0.063 degrees. The large error is due to numerical precision. When we enable quadruple precision, the analysis is much slower, however the phase is now 0.072 degrees, much as we would expect for a result obtained without de-embedding.
The quadruple precision option in Sonnet causes calculation of the couplings between subsections to take place in quadruple precision. This is where the difference between two large numbers actually occurs. Once calculated, the result is truncated to double precision and the resulting matrix filled and inverted in double precision. With Quadruple precision, this structure gives good results down well into the 100 kHz range.
As a general rule with Sonnet, when working with micron sized cells (and especially when using vias) in the low single GHz range, consider using quadruple precision. If you are ever working with small meshes at lower frequencies with some other electromagnetic tool, the short length via can provide guidance as to what can be done and what can't.
On to Chapter 8 - Lossy Ground Plane and Lossy Dielectric Tests
