Sonnet Suites - RFIC Via Array Simplification
New technology for efficient simulation of micro via interconnects
- Maps micro via arrays to simulation via models that are efficient for EM analysis
- Automatic mapping with metal definitions that are consistent with RFIC design flows
- Via simplification is automated for GDSII, DXF and Gerber Imports and EDA Framework APIs for Cadence Virtuoso, Agilent ADS and AWR Microwave Office
In Release 13, Sonnet’s GDSII, DXF and Gerber Imports and EDA Framework APIs (Cadence Virtuoso, Agilent ADS and AWR Microwave Office) have the ability to simplify via array structures, such as those commonly found in silicon RFIC processes.
Today’s RFIC processes employ large arrays of vias for creating layer-to-layer interconnects, and for developing multilayer transmission line metal “stacks” to reduce losses. These via arrays, often composed of thousands of tiny vias, create special challenges for full wave EM solver meshing. Meshing each individual via for simulation leads to very high memory requirements due to the many small physical features.
In Release 13, micro via array simplification technology is introduced to accurately model via array interconnects in a highly efficient composite manner. The simplification comes in the form of a new via fill type defined for the EM solver. The simplification is automated and accessible in our GDSII import, as well as in our RF EDA framework interfaces. Multi-layer planar metal stacks (such as those used in silicon RFIC inductors, baluns and transformers) can now be efficiently simulated in Sonnet without manual model adjustments.
Sonnet's new via simplification feature replaces micro via arrays automatically with composite via structures that mesh much more efficiently, while providing electrically correct simulation results for DC, low frequency and high frequency behavior. The simplified vias in Sonnet result in dramatically faster simulation models with accurate DC, low and high frequency response.